The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Memory integrated circuits (ICs) comprise memory arrays. The memory arrays include memory cells arranged in rows and columns. The memory cells in the rows and columns are addressed by word lines (WLs) that select the rows and bit lines (BLs) that select the columns. The memory ICs comprise WL and BL decoders that select the WLs and BLs, respectively, during read/write operations.
Referring now to FIG. 1, an IC 10 comprises a memory array 12, a WL decoder 16, a BL decoder 18, and a read/write (R/W) control module 19. The memory array 12 comprises memory cells 14 arranged in rows and columns as shown. The WL and BL decoders 16, 18 select the WLs and BLs, respectively, depending on the addresses of the memory cells 14 selected during read/write operations. The R/W control module 19 reads and writes data in the selected memory cells 14.
The memory cells 14 may include cells of nonvolatile memory such as NAND or NOR flash memory. Each memory cell 14 may be programmed to store N binary digits (bits) of information, where N is an integer greater than or equal to 1. Accordingly, each memory cell 14 may have 2N states. To store N bits per cell, each memory cell 14 may comprise a transistor having 2N programmable threshold voltages (hereinafter threshold voltages). The 2N threshold voltages of the transistor represent the 2N states of the memory cell 14, respectively. For example only, the transistor may include a floating-gate field-effect transistor (FET) or a silicon-oxide nitride-oxide semiconductor (SONOS) FET.
Referring now to FIGS. 2A-2C, a memory cell 14-i may comprise a transistor 50 having a threshold voltage VT. In FIG. 2A, the transistor 50 may comprise a floating gate G (hereinafter gate G), a source S, and a drain D. In FIG. 2B, a graph of drain current (ID) versus gate-to-source voltage (VGS) of the transistor 50 is shown. Typically, the threshold voltage VT of the transistor 50 is an intercept on the VGS axis for a predetermined value of the drain current. In other words, the threshold voltage VT is a value of VGS that generates the predetermined drain current. The predetermined drain current may also be called a reference current or a threshold current. The value of the predetermined drain current depends on the value of the threshold voltage VT. The amount of charge stored in the gate G during a write operation determines the value of threshold voltage VT, the value of the corresponding predetermined drain current, and the state of the memory cell 14-i. Typically, the threshold voltage VT and the corresponding predetermined drain current are proportional to the amount of charge stored in the gate G.
In FIG. 20, for example, the transistor 50 may have two programmable threshold voltages VT1 and VT2 depending on the amount of charge stored in the gate G. When the amount of charge stored in the gate G is Q1, the threshold voltage of the transistor 50 is VT1. When the amount of charge stored in the gate G is Q2, the threshold voltage of the transistor 50 is VT2. Depending on the amount charge stored in the gate G, a gate voltage (i.e., VGS) having a value greater than or equal to VT1 or VT2 may be necessary to turn on the transistor 50 (i.e., to generate the predetermined drain current).
The state of the memory cell 14 is read by measuring the threshold voltage VT of the transistor 50. The threshold voltage VT is measured by applying the gate voltage to the gate G and sensing the drain current. The drain current is sensed by applying a small voltage across the source S and the drain D of the transistor 50.
When the gate voltage is less than the threshold voltage VT, the transistor 50 is off, and the drain current is low (approximately zero). When, however, the gate voltage is greater than or equal to the threshold voltage VT, the transistor 50 turns on, and the drain current becomes high (i.e., equal to the predetermined drain current corresponding to the VT). The value of the gate voltage that generates the high drain current represents the threshold voltage VT of the transistor 50.
In a memory array, if independent gate control were possible, a binary search algorithm can be used to measure the threshold voltage. The threshold voltage could be measured to N-bit accuracy in N search cycles, where N is an integer greater than 1. But in a typical memory array, all transistors whose threshold voltages are to be measured at approximately the same time have their gates attached to the same word lines. Thus, independent gate control necessary for independent binary search algorithm is not possible. Accordingly, for an N-bit threshold voltage measurement, the most convenient way to measure the threshold voltages of all transistors is by stepping through (2N−1) voltages on the word lines, and determining the threshold voltage of the transistors when the drain currents of the transistors first exceed a predetermined (preprogrammed) value.
Referring now to FIGS. 3A-3D, the threshold voltage of the transistor 50 is measured as follows. For example only, the transistor 50 may have four threshold voltages VT1 to VT4, where VT1<VT2<VT3<VT4. Accordingly, the memory cell 14-i may have one of four states 00, 01, 10, and 11.
In FIG. 3A, the R/W control module 19 comprises a staircase voltage generator 20 and current sensing amplifiers 22. The number of current sensing amplifiers is equal to the number of bit lines. For example, when the IC 10 comprises B bit lines, the current sensing amplifiers 22 include B current sensing amplifiers for B bit lines, respectively, where B is an integer greater than 1.
In FIG. 3B, the WL decoder 16 selects a word line comprising memory cells 14-1, 14-2, . . . , 14-i, . . . , and 14-n (collectively memory cells 14) when the states of the memory cells are to be determined. Each of the memory cells 14 includes a transistor similar to the transistor 50. The transistors are shown as capacitances C that store the charge in the gates.
When a read operation begins, the staircase voltage generator 20 supplies a staircase voltage to the WL decoder 16. The WL decoder 16 inputs the staircase voltage to the selected word line. Accordingly, the staircase voltage is applied to the gates of the transistors on the selected word line.
The current sensing amplifiers 22 include one current sensing amplifier for each bit line. For example, a current sensing amplifier 22-i communicates with a bit line BL-i and senses the drain current that flows through the transistor 50 of the memory cell 14-i. The current sensing amplifier 22-i senses the drain current by applying a small voltage across the source and the drain of the transistor 50. Each current sensing amplifier senses the drain current that flows through the respective one of the transistors of the memory cells 14. The R/W control module 19 measures the threshold voltages of the transistors based on the drain currents sensed by the respective current sensing amplifiers 22.
In FIG. 3C, the staircase voltage can be increased in (2N−1) steps when the memory cells 14 have 2N states each. In the example shown, N=2. Accordingly, the staircase voltage that can be increased in three steps.
Specifically, in a first step, the staircase voltage can be increased from zero to a first voltage that is slightly greater than VT1. In a second step, the staircase voltage can be increased from the first voltage to a second voltage that is slightly greater than VT2. In a third step, the staircase voltage can be increased from the second voltage to a third voltage that is slightly greater than VT3. At each step, the current sensing amplifiers 22 measure the drain currents that flow through the memory cells 14. The first, second, and third voltages are sequentially applied to the gates of the transistors until the threshold voltages of the transistors are determined based the sensed drain currents.
More specifically, in the first step, the first voltage is applied to the gates of the transistors. The current sensing amplifiers 22 sense the drain currents that flow through the transistors. For example, if the drain current flowing through the transistor 50 is high, then the threshold voltage of the transistor 50 is VT1, and the state of the memory cell 14-i is the first state (e.g., 00). If, however, the sensed drain current is low, then the threshold voltage of the transistor 50 is greater than VT1, and the state of the memory cell 14-i is other than the first state.
The threshold voltage of the transistor 50 may be VT2, VT3, or VT4. The state of the memory cell 14-i may be the second state (e.g., 01), the third state (e.g., 10), or the fourth state (e.g., 11). Accordingly, at least one and at most two more attempts to determine the threshold voltage of the transistor 50 are necessary.
Next, in the second step, the staircase voltage is stepped up from the first to the second voltage, and the second voltage is applied to the gates of the transistors. The current sensing amplifiers 22 sense the drain currents that flow through the transistors. For example, if the drain current flowing through the transistor 50 is high, then the threshold voltage of the transistor 50 is VT2, and the state of the memory cell 14-i is the second state.
If, however, the sensed drain current is low, then the threshold voltage of the transistor 50 is greater than VT2, and the state of the memory cell 14-i is neither the first state nor the second state. The threshold voltage of the transistor 50 may be VT3 or VT4. The state of the memory cell 14-i may be the third state or the fourth state. Accordingly, at least one more attempt to determine the threshold voltage of the transistor 50 is necessary.
Finally, in the third step, the staircase voltage is stepped up from the second to the third voltage, and the third voltage is applied to the gates of the transistors. The current sensing amplifiers 22 sense the drain currents flowing through the transistors. For example, if the drain current flowing through the transistor 50 is high, then the threshold voltage of the transistor 50 is VT3, and the state of the memory cell 14-i is the third state. If, however, the sensed drain current is low, then the threshold voltage of the transistor 50 is VT4, and the state of the memory cell 14-i is the fourth state.
Thus, (2N−1) attempts or trials are necessary to measure the threshold voltages of the transistors having 2N threshold voltages each. That is, (2N−1) attempts are necessary to measure the states of the memory cells 14 when the memory cells 14 have 2N states each. As the value of N increases, the number of attempts necessary to measure the threshold voltages also increases. Consequently, the time taken to measure the threshold voltages (and the states of the memory cells 14) increases as the value of N increases.
Additionally, the transistors of the memory cells 14 and segments of the selected WL between adjacent memory cells 14 act as capacitances and resistances, respectively, as shown in FIG. 3B. Accordingly, the selected WL comprises a series of RC circuits as shown. As the distance of the memory cell 14-i increases from the WL decoder 16, the settling time of the transistor 50 increases. The settling time is the time taken by the VGS of the transistor 50 to settle to the staircase voltage input to the gate G.
For example, in FIG. 3C, the settling time Ts1 of VGS of a first transistor on the selected word line is shown. The first transistor is a transistor of the memory cell 14-1 that is adjacent to the WL decoder 16. When the first voltage is applied to the gate of the first transistor, the VGS of the first transistor rises and settles to a value equal to the first voltage after time Ts1. The current sensing amplifier that measures the drain current that flows through the first transistor must wait for a time period equal to Ts1 for the VGS to settle before measuring the drain current. The step of waiting for the settling time before sensing the drain current is repeated for each subsequent stepped up voltage if necessary until the threshold voltage of the first transistor is determined.
In FIG. 3D, the settling time Tsn of VGS of a last transistor on the selected WL is shown. The last transistor is a transistor of the last memory cell 14-n. When the first voltage is applied to the gates of the transistors on the selected WL, the VGS of the last transistor rises and settles to a value equal to the first voltage after time Tsn, where Tsn>>Ts1. The current sensing amplifier that senses the drain current that flows through the last transistor waits for a time period equal to Tsn before measuring the drain current. The step of waiting for the settling time before sensing the drain current is repeated for each subsequent stepped up voltage if necessary until threshold voltage of the last transistor is determined. As can be appreciated, the value of Tsn and the time taken to measure the threshold voltage of the last transistor (and the state of the last memory cell 14-n) increases as the number of memory cells 14 on the word line increases.
As the memory capacity of the memory ICs increases, the value of N (i.e., the number of bits per memory cell) and/or the number of memory cells per word line increases. Accordingly, the value of (2N−1) and/or Tsn increases. Consequently, the time taken to measure the threshold voltages of the transistors (and the states of the memory cells 14) on the selected word line increases.
Since today's memory ICs can be quite large in capacity, the loading and thus the settling time constant for the gate control voltage can be quite large. For example, in a 2 GB NAND memory IC, each row in the memory array may contain more than 100 thousands memory transistors. Together with a relatively high word line resistance, the word line settling time is typically in the range of microseconds to tens of microseconds. Bit line sensing cannot be done until the control voltage applied to the gate has settled sufficiently. The bit line current sensing amplifiers usually have to wait for multiple time constants of the word line control voltage before starting to sense the drain current via the bit line.
Presently, the highest maximum number of bits stored in the form of threshold voltage is two. For read-sensing, the number of bits required for digitization is typically the same as the number of bits stored in the threshold voltage values. Thus, for example, a total of (22−1)=3 control voltages need to be applied for digitization purpose. The digitizing speed is thus no less than 3 times the time required for the row-line to adequately settle.
To store more bits in the form of the threshold voltage of a transistor, the digitizer resolution will also need to be increased. Increasing the storage bits from 2 to 3 per transistor increases the number of control voltages from 3 to 7. For memory systems that uses soft information and signal processing to improve data error rate, even more bits are required from the read-digitizer. Accordingly, if the read-digitization is limited by the word line settling time, the read time of high resolution memory devices will increase exponentially.